Programmable logic devices, or PLDs, are general-purpose circuits that can be programmed by an end user to perform one or more selected functions. Complex PLDs typically include a number of programmable logic elements and some programmable routing resources. Programmable logic elements have many forms and many names, such as CLBs, logic blocks, logic array blocks, logic cell arrays, macrocells, logic cells, and functional blocks. Programmable routing resources also have many forms and many names.
FIG. 1A (prior art) is a block diagram of a field-programmable gate array (FPGA) 100, a popular type of PLD. FPGA 100 includes an array of identical CLB tiles 101 surrounded by edge tiles 103-106 and corner tiles 113-116. Columns of random-access-memory (RAM) tiles 102 are positioned between two columns of CLB tiles 101. Edge tiles 103-106 and corner tiles 113-116 provide programmable interconnections between tiles 101-102 and input/output (I/O) pins (not shown). FPGA 100 may include any number of CLB tile columns, and each tile column may include any number of CLB tiles 101. Although only two columns of RAM tiles 102 are shown here, more or fewer RAM tiles might also be used. The contents of configuration memory 120 defines the functionality of the various programmable resources.
FPGA resources can be programmed to implement many digital signal-processing (DSP) functions, from simple multipliers to complex microprocessors. For example, U.S. Pat. No. 5,754,459, issued May 19, 1998, to Telikepalli, and incorporated by reference herein, teaches implementing a multiplier using general-purpose FPGA resources (e.g., CLBs and programmable interconnect). Unfortunately, DSP circuits may not make efficient use of FPGA resources, and may consequently consume more power and FPGA real estate than is desirable. For example, in the Virtex family of FPGAs available from Xilinx, Inc., implementing a 16×16 multiplier requires at least 60 CLBs and a good deal of valuable interconnect resources.
FIG. 1B (prior art) depicts an FPGA 150 adapted to support DSP functions in a manner that frees up general-purpose logic and resources. FPGA 150 is similar to FPGA 100 of FIG. 1A, like-numbered elements being the same or similar. CLB tiles 101 are shown in slightly more detail to illustrate the two main components of each CLB tile, namely a switch matrix 120 and a CLB 122. CLB 122 is a well-known, individually programmable CLB such as described in the 2002 Xilinx Data Book. Each switch matrix 120 may be a programmable routing matrix of the type disclosed by Tavana et al. in U.S. Pat. No. 5,883,525, or by Young et al. in U.S. Pat. No. 5,914,616 and provides programmable interconnections to other tiles 101 and 102 in a well-known manner via signal lines 125. Each switch matrix 120 includes an interface 140 to provide programmable interconnections to a corresponding CLB 122 via a signal bus 145. In some embodiments, CLBs 122 may include direct, high-speed connections to adjacent CLBs, for instance, as described in U.S. Pat. No. 5,883,525. Other well-known elements of FPGA 100 are omitted from FIG. 1B for brevity.
In place of RAM blocks 102 of FIG. 1A, FPGA 150 includes one or more columns of multi-function tiles 155, each of which extends over four rows of CLB tiles. Each multi-function tile includes a block of dual-ported RAM 160 and a signed multiplier 165, both of which are programmably connected to the programmable interconnect via respective input and output busses 170 and 175 and a corresponding switch matrix 180. FPGA 150 is detailed in U.S. Pat. No. 6,362,650 to New et al. entitled “Method and apparatus for incorporating a multiplier into an FPGA,” which is incorporated herein by reference.
FPGA 150 does an excellent job of supporting DSP functionality. Complex functions must make use of general-purpose routing and logic, however, and these resources are not optimized for signal processing. Complex DSP functions may therefore be slower and more area intensive than is desirable. There is therefore a need for DSP circuitry that addresses consumer demand for ever faster speed performance without sacrificing the flexibility afforded by programmable logic.